1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same.
2. Related Art
A logic circuit such as an SRAM or a clocked inverter is required to be reduced in operating voltage and to be increased in speed. In the SRAM, a reduction of bit line capacitance is contributed to a high-speed operation more greatly than a reduction of word line capacitance (see Y. Tsukamoto et al.: SSDM 2003, pages 22 and 23). The bit line capacitance includes the wiring capacitance of the bit line and the parasitic capacitance of a transistor of a transfer gate connected to the bit line.
The parasitic capacitance of the transfer gate consists of a junction capacitance of the source or the drain of the transfer gate. A reduction of the junction capacitance of the diffusion layer in the transfer gate is important to realize a high-speed operation of an SRAM. In particular, when the SRAM is operated by a lower power supply voltage, the SRAM is considerably influenced by the junction capacitance of the diffusion layer.
An impurity profile of the diffusion layer of the transfer gate may be changed to reduce the junction capacitance. However, the junction capacitances of a driver transistor (pull-down transistor) and a load transistor (pull-up transistor) used in an inverter part of the SRAM also decrease. This deteriorates data holding capability to cause a soft error by cosmic ray irradiation.
In a logic circuit such as a clocked inverter circuit, when the impurity profile of the diffusion layer of a transistor is changed to realize a high-speed operation, the resistance to noise (noise margin) is deteriorated disadvantageously due to lower node capacitance.
Therefore, there is provided a semiconductor integrated circuit device which has high resistance to a soft error and noise while reducing the junction capacitance of the transistor.